The present invention relates to a circuit design generally and, more particularly, to datapath bitslice technology.
Conventional designs for complex circuits begin with defining the functionality of the circuit in a high level hardware description language, such as a register transfer language (RTL). From an RTL file, the circuit is synthesized to a gate level design in hardware. Typical existing RTL defined circuits have a variety of clocks used across various modules of the circuit. Any digital logic within a module that is not running at an upper speed limit of the fastest clock, especially logic in a datapath, can have an inefficient layout in terms of gate count and thus silicon size. The datapath is typically the part of the design that has a number of bits in width on which processing is performed. Therefore, one or more modules not leveraging faster clocks that are typically available are not optimized in size or gate count.
The present invention concerns a method for reducing circuit gate count. The method generally comprises the steps of (A) generating a new file from a source file and a parameter file, wherein the source file comprises a first circuit defined in a hardware description language, the new file comprises a second circuit defined in the hardware description language, the parameter file comprises a second clock frequency for the second circuit that is faster than a first clock frequency for the first circuit, and the first circuit is functionally equivalent to the second circuit, (B) generating a first gate count by synthesizing a first design from the source file, (C) generating a second gate count by synthesizing a second design from the new file and (D) generating a statistic by comparing the first gate count and power to the second gate count and power.
The objects, features and advantages of the present invention include providing a datapath bitslice technology that may provide (i) generation of reduced size logic without changing functionality, (ii) operation at a faster clock rate, (iii) an architecture for datapath bitslicing, (iv) constraint features within the datapath bitslice technology and/or (v) automated iteration of circuit size reduction.